Senior Digital Verification Engineer
The Mixed Signal Development Group (MSDG) looking to grow our design group within Microchip’s Penang facilities. We are seeking an individual with verification experience to expand this group and build advanced high-speed SERDES and PHY designs in FinFET technologies.
Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments
Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog / UVM
Writing block level Verilog / System-Verilog directed test-benches and supporting verification team with debug.
Analyzing Functional, Code, and Test Plan Coverage
Implementing Assertions, Checkers, Generators, and Monitors
Leadership opportunities are available
Bachelor’s or higher degree in Electrical Engineering
Work experience : 5+ years of ASIC development or verification experience
Strong working knowledge in one or more of the following disciplines; SystemVerilog, UVM, OVM, VMM.
Previous experience in Writing / Implementing / Reviewing Verification Plans.
Previous experience with SystemVerilog Assertions (SVA), Constrained Random Verification, and Functional coverage.
Experience in automation and scripting with languages such as Python / Perl / TCL / Shell